The computer electronics industry uses electronic packaging substrates on which electrical devices, such as semiconductor chips, are electrically mounted. The trend in the electronics industry is to use multilevel thin film structures on the electronic devices and substrates for providing electrical interconnection to the circuits on the chips and the substrates. State of the art multilevel thin film structures are preferably formed from thin layers of polymeric material with electrical conductors disposed therebetween and electrical conducting vias disposed through the thin film polymeric layers to provide electrical interconnection of the conductors on different levels of the multilevel structure.
In order to reduce fabrication time and hence the cost of these thin film structures a parallel fabrication process rather than a sequential process is preferred
In a sequential process, an electronic substrate, such as, a semiconductor chip or packaging substrate is provided. A polymer layer is disposed on a surface of the substrate. On the exposed surface of the polymer layer a patterned layer of electrical conductors is disposed. Another layer of polymeric material is disposed on the electrically conducting layer. Electrically conducting vias are formed through the second polymeric layer. A second layer of patterned electrical conductors are disposed on the exposed surface of the second polymeric layer. This process is continued until the desired number of layers of electrical conductors with polymeric layers disposed therebetween having electrically conducting vias to electrically interconnect adjacent electrically conducting layers is formed. In this sequential process, any one of the polymeric layers or the electrically conducting layers or the electrically conducting vias can have a defect which renders the finally formed structure is unusable.
It is preferable to build the multilayer structure in a parallel process wherein a group of planar subassemblies are fabricated and tested and then electrically assembled to form the multilevel thin film structure. The subassemblies have on both surfaces thereof an array of contact pads which are typically circular or square. A first substrate is disposed in contact with a second substrate so that an array of contact locations on the first substrate is aligned with an array of contact locations on the second substrate with corresponding contact locations joined in electrical contact.
The center of the first substrate is aligned to the center of the second substrate to within a manufacturing tolerance. This manufacturing tolerance results in a statistical distribution of the overlap of the contact location on the first substrate with corresponding contact locations on the second substrate. Additionally, due to stress in the substrate or shrinkage during formation of the substrate, there may be some distortion in the contact locations. If the contact locations are circular or square, they must have a minimum size dictated by the tolerance of the alignment of the first and second substrates and the distortion. There is a capacitance between this contact location and the electrical conductors in the substrate above and beneath the contact pad. This is a parasitic capacitance which causes delays in signals propagated through the multilevel structure. To reduce this parasitic capacitance the dielectric layer between the contact pad and the electrical conductors beneath the pad must have an increased thickness. This thickness adds to the manufacturing cost by requiring additional material, a different processing step than used to fabricate the other dielectric layers, additional defects due to the thickness and additional stress in the composite structure.